Part Number: DRV8307
We are using the DRV 8307 to interface to reciprocating piston pump.DRV 8307 is controlled by the FPGA.During testing we follow these steps:
1. Program the FPGA
2. Send 20% PWM-DC input to the DRV8307.We see the pump running at 20% PWMDC.Then reconfigure/reset the FPGA,(we expect the pump to stop).The pwm input of pump driver is low and pump stops.
3.Repeat steps 1 & 2 for for different PWMDC values(30%,40% upto 100%).
For all duty cycles except 100% ,the pump stops when FPGA is reconfigured or reset.This is expected,so no problem here.
The problem starts when 100% PWMDC input is sent to DRV8307 ,the pump starts running at 100% PWMDC.This is fine. Now press the reconfig/reset button on fpga board,we expect the pump to stop running.but pump doesn't stop.It continues running at 100% PWMDC,when FPGA image is not there.We probed the pwm output of FPGA(input of DRV8307) ,it is low.Then we probed the drive_en (active low) input of DRV 8307.It is low.We expect the pump to stop when the FPGA is reset/reconfigured,but pump continues to run at 100%PWM DC .This is happening only for 100%PWM DC.Any suggestions why?