DRV8308: SPI SCLK Timing

Part Number: DRV8308

The DRV8308 datasheet specifies a minimum SPI clock (SCLK) cycle time of 62 nS (~16 MHz).  The evaluation board runs the clock at 1 MHz.  On our custom hardware, I've found that transfers do not work properly for frequencies above ~2 MHz.  This is well below the specified limit.  Is this a known deficiency?

Thanks.