Hi Simone,
Have you read section 8.1.1 of the revision F datasheet:
The DRV8301 gate drivers may not correctly power up if a voltage greater than 8.5 V is present on any SH_X pin
when EN_GATE is brought logic high (device enabled) after PVDD1 power is applied (PVDD1 > PVDD_UV).
This sequence should be avoided by ensuring the voltage levels on the SH_X pins are less than 8.5 V when the
DRV8301 is enabled through EN_GATE.
Do you have this condition?
Have you read section 8.1.1 of the revision F datasheet:
The DRV8301 gate drivers may not correctly power up if a voltage greater than 8.5 V is present on any SH_X pin
when EN_GATE is brought logic high (device enabled) after PVDD1 power is applied (PVDD1 > PVDD_UV).
This sequence should be avoided by ensuring the voltage levels on the SH_X pins are less than 8.5 V when the
DRV8301 is enabled through EN_GATE.
Do you have this condition?