Hi Eray,
Assuming this image is a high side FET and the low side FET is off, this behavior could be expected.
Are you looking at the gate of a high side FET? What is the gate of the corresponding low side FET?
Please look at section 7.2. The gate of the high side FET is either connected to the PHASE (SH_x) voltage when off or the VCPH voltage when on.
The gate of the low side FET is connected to either GND when on or VCP_LSD when off.
Assuming this image is a high side FET and the low side FET is off, this behavior could be expected.
Are you looking at the gate of a high side FET? What is the gate of the corresponding low side FET?
Please look at section 7.2. The gate of the high side FET is either connected to the PHASE (SH_x) voltage when off or the VCPH voltage when on.
The gate of the low side FET is connected to either GND when on or VCP_LSD when off.