Hi Rick,
1) R(sense) is 40mR as I wrote above.
2) Signal reference is directly at the gate of the FET, GND was connected to the GND supply input of the board. I can do additional measurements tomorrow if required.
3) The temperature of the FETs is the same than for the PCB, around 70°C
4) The ground plane on the top side is only .55x0.55", interrupted by traces and vias. But there are ground layers on the other three layers connected with by 12 0.4mm vias in total. I will do optimisation at this point, the fan-out isn't very good here.
5) We do not draw current from the 5V regulator. /Sleep is pulled up high by a high impedance voltage divider plus a 5.1V zener to ensure auto-power up. The rest of the board (mainly a small micro) is powered by a seperate linear regulator.
I will try your tipps tomorrow. Series resistors on low side FETs are 47R. At first we tried without, but had problems with predriver faults.
With kind regards,
Thorsten Ostermann
1) R(sense) is 40mR as I wrote above.
2) Signal reference is directly at the gate of the FET, GND was connected to the GND supply input of the board. I can do additional measurements tomorrow if required.
3) The temperature of the FETs is the same than for the PCB, around 70°C
4) The ground plane on the top side is only .55x0.55", interrupted by traces and vias. But there are ground layers on the other three layers connected with by 12 0.4mm vias in total. I will do optimisation at this point, the fan-out isn't very good here.
5) We do not draw current from the 5V regulator. /Sleep is pulled up high by a high impedance voltage divider plus a 5.1V zener to ensure auto-power up. The rest of the board (mainly a small micro) is powered by a seperate linear regulator.
I will try your tipps tomorrow. Series resistors on low side FETs are 47R. At first we tried without, but had problems with predriver faults.
With kind regards,
Thorsten Ostermann