Hello Yamamoto-san,
Thank you very much for the diagram I understand the question now.
For the propagation delay question:
I have confirmed that low side delay is similar to high side delay 200ns.
For the PWM propagation question:
- The output waveform will have a slight variation if your resolution is 12.2ns. This is due to the internal core logic.
- There is an internal 25Mhz glitch clock, so the variation would come from the moment PWM switches high/low or low/high to the next sampling of the glitch clock which is every 40 ns.
Thank you very much for the diagram I understand the question now.
For the propagation delay question:
I have confirmed that low side delay is similar to high side delay 200ns.
For the PWM propagation question:
- The output waveform will have a slight variation if your resolution is 12.2ns. This is due to the internal core logic.
- There is an internal 25Mhz glitch clock, so the variation would come from the moment PWM switches high/low or low/high to the next sampling of the glitch clock which is every 40 ns.
