Hi Shimizu-san,
Sorry for the delay.
>What do you mean "Design value or Guaranteed value"?
-> 6A is checked at ATE? or 6A is theoretical value?
Are there devices which has the value of under 6A as Iocp?
>>> This value is tested at ATE.
and I add a question.
Add Q: Absolute Maximum Ratings in datasheet, shows below.
"Peak motor drive output current, t < 1 μS"
Does this mean that device has damage by being applied over 6A current for the period of time of over 1us?
>>> The device has internal protection for this condition. Please note section 7.3.6.1 of the datasheet:
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is removed and re-applied.
Sorry for the delay.
>What do you mean "Design value or Guaranteed value"?
-> 6A is checked at ATE? or 6A is theoretical value?
Are there devices which has the value of under 6A as Iocp?
>>> This value is tested at ATE.
and I add a question.
Add Q: Absolute Maximum Ratings in datasheet, shows below.
"Peak motor drive output current, t < 1 μS"
Does this mean that device has damage by being applied over 6A current for the period of time of over 1us?
>>> The device has internal protection for this condition. Please note section 7.3.6.1 of the datasheet:
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is removed and re-applied.