RE: DRV8301: DRV8301 showing no fault still not working

Hi Jesal,

Sorry, I missed the fact that nSCS was low through out the two transactions. At the end of 16 clocks, nSCS should be set to a logic high to frame the transaction.

Please see the post: e2e.ti.com/.../1723924 as an example.

The datasheet also describes a valid SPI frame in the SPI section.