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RE: DRV8833: DRV8833 UVLO operation

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Hi Cafain,

[quote user="cafain"]

1.When the VM rises above the UVLO threshold, please tell me the delay time until motor drive operation resumes?

[/quote]

Assuming nSLEEP is set to  a logic one when VM rises, the delay time should be less than 1ms.

[quote user="cafain"]

2.When UVLO is detected, all circuits in the device are invalidated and all internal logic is reset,
   is it to read the rising edge of the new control signal?

[/quote]

The UVLO circuit is to ensure the device voltage is enough to ensure proper operation.

[quote user="cafain"]

3.If the control terminal remains ON, if the VM voltage has a voltage variation of 90 mV (VHYS) with respect to the VUVLO value,
   it is considered that the motor drive output repeats ON and OFF, but is this mistake correctly?

[/quote]

I do not understand this question. Can you explain your concern?


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