Hi Tao_2199,
[quote user="Tao_2199"]
(1) When they configured VREG and EN_GATE at power on, nFault is toggled with about 64us period.
(It seems that when EN_GATE is high, nFault stop to toggle and goes to high.)
Please attached file.
According to datasheet(page32:7.4.1 Power Up Sequence),
"nFAULT will be driven low to indicate that the device has not reached the VPVDD_UVLO2 threshold."
In case of thier application, nFault output is correct? Or something problem is happened while power on?
[/quote]
Was the SPI register read to determine the cause of the warning? What value was read?
What cause the nFAULT to stop toggling?
[quote user="Tao_2199"]
(2)When INH and INL are set Low at starting motor drive, GHA output is not Low. (It’s High.)
Please attached file.
Is it correctly operation? Can GHA be set as Low(0V) at INH/INL=Low?
[/quote]
Please note section 7.2 of the datasheet. When GHx is low, this means the VGS voltage across the high side FET = 0. The high side gate is connected to the phase pin.