Mark,
Good news! I talked to the IC designer for this part, and there should be no issues for adding the resistor on CPL as you suggest.
The only concern with adding the resistor in series with the CPL gate would be the voltage drop across the 100ohm resistor. This should be fine for lower I_DRIVE settings. The biggest impact would be that I*R voltage drop on the 100-Ohm resistor could impact the Rds(on) of your external high-side FETs when you drive them at slightly lower gate-drive voltage.
That said, if you are seeing acceptable performance from you system, you should be fine!
Good news! I talked to the IC designer for this part, and there should be no issues for adding the resistor on CPL as you suggest.
The only concern with adding the resistor in series with the CPL gate would be the voltage drop across the 100ohm resistor. This should be fine for lower I_DRIVE settings. The biggest impact would be that I*R voltage drop on the 100-Ohm resistor could impact the Rds(on) of your external high-side FETs when you drive them at slightly lower gate-drive voltage.
That said, if you are seeing acceptable performance from you system, you should be fine!