Hi Nam, Sang-il,
Sorry for the delay. We were not to duplicate your findings.
When GVDD and VDD = 12V, the outputs were measured to be 560mV. PVDD was measured to be 330mV. PVDD is following the OUT_x pins because the body diode of the high side FET is conducting. There are internal paths from GVDD to the output and through the body diode to PVDD.
If you want PVDD to be 0V, it is recommended to turn off GVDD/VDD when turning off PVDD.
Sorry for the delay. We were not to duplicate your findings.
When GVDD and VDD = 12V, the outputs were measured to be 560mV. PVDD was measured to be 330mV. PVDD is following the OUT_x pins because the body diode of the high side FET is conducting. There are internal paths from GVDD to the output and through the body diode to PVDD.
If you want PVDD to be 0V, it is recommended to turn off GVDD/VDD when turning off PVDD.
