Hi Mak,
With the inputs configured as stated, the outputs should be disabled. Have you measured resistances between PVDD, GVDD, VDD, VREG, BST_x and GND? Is it possible to slowly raise the voltage on GVDD, VDD, PVDD and determine the current?
Do you have a load connected after the power is switched on? If the load is connected, please disconnect the load and try enabling the outputs. Do you get the same results?
It is recommended to turn the low side FET on for at least 50ns during each PWM cycle to avoid BST_UVP.
Once you move pass the existing issue, please note section 7.4 of the datasheet. In PFB mode setting RESET_AB/ or RESET_CD/ to low resets all four outputs.
With the inputs configured as stated, the outputs should be disabled. Have you measured resistances between PVDD, GVDD, VDD, VREG, BST_x and GND? Is it possible to slowly raise the voltage on GVDD, VDD, PVDD and determine the current?
Do you have a load connected after the power is switched on? If the load is connected, please disconnect the load and try enabling the outputs. Do you get the same results?
It is recommended to turn the low side FET on for at least 50ns during each PWM cycle to avoid BST_UVP.
Once you move pass the existing issue, please note section 7.4 of the datasheet. In PFB mode setting RESET_AB/ or RESET_CD/ to low resets all four outputs.