DRV8106-Q1: Usinng the SPI version

Tool/software:

I have the following queries regarding DRV8106S and would request your urgent attention for the same.

We are planning to use DRV8106S with independent High side and low side for motors as shown in attached image. We are planning to use Vsys(system voltage) between 25V to 30V.

1. Please have a review of the attached image of the circuit and provide your expert opinion. We would like to control two individual motors separately with same PWM at nHIZ1 and toggling IN1 to select high side or low side.
2. It is mentioned that significant difference should not be there between PVDD and Drain(7.3.5 section of datasheet). Incase I am using different voltages for PVDD and Drain what can be the possible difference?
3. As per my understanding the gate voltage is generated by the charge doubler with PVDD input and supplied directly. So, the max voltage I will get is PVDD + Vvcp. i.e, If I am using 15V PVDD, gate will have 15V+10.5V=25.5V at the input. Am I correct on this?