Hi Rick,
Thanks for a fast answer. The /OTW might be difficult to analyse in the circuit, but I agree it can clarify things up, so I'll do.
VDD and all GVDD_X pins are tied together, and connected to +12 V (50 uF input capacity). PVDD_X pins are also tied together, and connected to the DC bus (max. +48 V, with 20 uF capacity).
The /FAULT signal is directly connected to the highest priority interrupt input in the DSP, which react in a maximum of 50 ns. But, we have a 1 nF net capacity, and now I suspect that this might be causing the /FAULT signal to not reach the DSP. Which is the output impedance of the /FAULT pin?
Thanks a lot for your help!