Hi Shimizu,
nFAULT is not driven low directly based on nSLEEP. When in nSLEEP condition, the internal transistor of nFAUTL is on an undefined state, but the external pull up will still pull the nFAULT pin High.
When the device is just enterning nSLEEP, the VINT is going to off but the external cap will keep the VINT voltage for some time which can still drive the internal circuit. The nFAULT is going on down at this time because the VINT and charge pump voltage is dropping and UVLO asserted. But when the device goes into fully SLEEP mode, the nFAULT is pulled high by external pull up again. But when the device leaves the SLEEP mode, the VINT and charge pump voltage need some time to setup again, so the UVLO nFAULT comes out again just when the device wakes up. On P20 upper section, there is some description about this.
For the reason of the different behavior of 4us, 6us at -10C or 4us at -10C and 25C, one hypothesis is that the device is already taken the nSLEEP command when nSLEEP signal is > 500ns. But the SLEEP is recover soon. So it is possible that the device is not fully reset because the external cap of VINT maintained the internal logic. We don't see output current change in this case. But there will be a timing threshold that the device did a fully reset which makes more than 1ms to recover, so we can see the output current change. The reason why this timely threshold changes might because of the external cap capacitance change to the temperature change.
One simple way to verify the above theory is to change the VINT cap 2x bigger and redo the 4us 6us tests to see if this time changed as well. Sorry I'm on a visit and I could only do the verification early next week.
Best regards,
nFAULT is not driven low directly based on nSLEEP. When in nSLEEP condition, the internal transistor of nFAUTL is on an undefined state, but the external pull up will still pull the nFAULT pin High.
When the device is just enterning nSLEEP, the VINT is going to off but the external cap will keep the VINT voltage for some time which can still drive the internal circuit. The nFAULT is going on down at this time because the VINT and charge pump voltage is dropping and UVLO asserted. But when the device goes into fully SLEEP mode, the nFAULT is pulled high by external pull up again. But when the device leaves the SLEEP mode, the VINT and charge pump voltage need some time to setup again, so the UVLO nFAULT comes out again just when the device wakes up. On P20 upper section, there is some description about this.
For the reason of the different behavior of 4us, 6us at -10C or 4us at -10C and 25C, one hypothesis is that the device is already taken the nSLEEP command when nSLEEP signal is > 500ns. But the SLEEP is recover soon. So it is possible that the device is not fully reset because the external cap of VINT maintained the internal logic. We don't see output current change in this case. But there will be a timing threshold that the device did a fully reset which makes more than 1ms to recover, so we can see the output current change. The reason why this timely threshold changes might because of the external cap capacitance change to the temperature change.
One simple way to verify the above theory is to change the VINT cap 2x bigger and redo the 4us 6us tests to see if this time changed as well. Sorry I'm on a visit and I could only do the verification early next week.
Best regards,